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description these hall-effect latches are extremely temperature-stable and stress resistant sensor ics especially suited for operation over extended temperature ranges to 150c. superior high- temperature performance is made possible through a novel schmitt trigger circuit that maintains operate and release point symmetry by compensating for temperature changes in the hall element. additionally, internal compensation provides magnetic switchpoints that become more sensitive with temperature, hence offsetting the usual degradation of the magnetic field with temperature. the symmetry capability makes these devices ideal for use in pulse-counting applications where duty cycle is an important parameter. the three basic devices (A1225, a1227, and a1229) are identical except for magnetic switchpoints. each device includes on a single silicon chip a voltage regulator, hall-voltage generator, temperature compensation circuit, signal amplifier, schmitt trigger, and a buffered open-drain output to sink up to 25 ma. the on-board regulator permits operation with supply voltages of 3.8 to 24 v. the first character of the part number suffix determines the device operating temperature range. suffix l is for ?40c to 150c. two package styles provide a magnetically optimized package for most applications. suffix lt is a miniature sot89/ to-243aa transistor package for surface-mount applications, suffix ua is a three-lead ultra-mini-sip. both packages are lead (pb) free with 100% matte tin leadframe plating. A1225-ds features and benefits ? symmetrical switchpoints ? superior temperature stability ? operation from unregulated supply ? open-drain 25 ma output ? reverse battery protection ? activate with small, commercially available permanent magnets ? solid-state reliability ? small size ? resistant to physical stress ? enhanced esd structures result in 8 kv hbm esd performance without external protection components ? internal protection circuits enable 40 v load dump compliance without external protection components hall effect latch for high temperature operation packages: 3-pin sot89 (suffix lt) and 3-pin sip (suffix ua) functional block diagram not to scale A1225, a1227, and a1229 hall chopping logic amp anti-aliasing lp-filter tuned filter clock / logic regulator to all subcircuits vcc vout gnd
hall effect latch for high temperature operation A1225, a1227 and a1229 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com pin-out diagrams absolute maximum ratings characteristic symbol notes rating unit forward supply voltage v cc 30 v reverse supply voltage v rcc ?30 v output off voltage v out 30 v reverse output voltage v rout ?0.5 v continuous output current i out(sink) 25 ma operating ambient temperature t a range l ?40 to 150 oc maximum junction temperature t j (max) 165 oc storage temperature t stg ?65 to 170 oc terminal list table number name function 1 vcc input power supply 2 gnd ground 3 vout output signal 2 1 3 23 1 package lt package ua selection guide part number packing * package ambient temperature, t a b rp (min) (g) b op (max) (g) A1225llttr-t 7-in. reel, 1000 pieces/reel 3-pin sot89 surface mount ?40c to 150c ?300 300 A1225lua-t bulk, 500 pieces/bag 3-pin sip through hole a1227llttr-t 7-in. reel, 1000 pieces/reel 3-pin sot89 surface mount ?40c to 150c ?175 175 a1227lua-t bulk, 500 pieces/bag 3-pin sip through hole a1229llttr-t 7-in. reel, 1000 pieces/reel 3-pin sot89 surface mount ?40c to 150c ?200 200 a1229lua-t bulk, 500 pieces/bag 3-pin sip through hole *contact allegro ? for additional packaging options.
electrical characteristics valid at t a = ?40c to 150c, c bypass = 0.1 f, v cc = 12 v; unless otherwise noted characteristics symbol test conditions min. typ. 1 max. unit 2 electrical characteristics supply voltage v cc operating; t j 165c 3.8 24 v supply current i cc b < b rp (output off) ? ? 6 ma b > b op (output on) ? ? 6 ma supply zener voltage v z(sup) i cc = 9 ma, t a = 25c 28 ? ? v reverse battery current i z(sup) v rcc = ?28 v, t a = 25c ? 5 ? ? ma power-on time 3 t po ??12 s power-on state pos b < b op ? high ? ? chopping frequency f chop ? 400 ? khz output stage characteristics output saturation voltage v out(sat) i out = 20 ma ? 175 400 mv output leakage current i off v out = 24 v, b < b rp ?< 110 a output rise time 3,4 t r r l = 820 , c l = 20 pf ? 200 2000 ns output fall time 3,4 t f r l = 820 , c l = 20 pf ? 200 2000 ns output zener voltage v z(out) i out = 3 ma, t a = 25c 30 ? ? v magnetic characteristics operate point b op A1225 t a = 25c 170 ? 270 g over operating temperature range 140 ? 300 g a1227 t a = 25c 50 ? 150 g over operating temperature range 50 ? 175 g a1229 t a = 25c 100 ? 180 g over operating temperature range 80 ? 200 g release point b rp A1225 t a = 25c ?270 ? ?170 g over operating temperature range ?300 ? ?140 g a1227 t a = 25c ?150 ? ?50 g over operating temperature range ?175 ? ?50 g a1229 t a = 25c ?180 ? ?100 g over operating temperature range ?200 ? ?80 g hysteresis (b op ? b rp )b hys A1225 t a = 25c 340 ? 540 g over operating temperature range 280 ? 600 g a1227 t a = 25c 100 300 g over operating temperature range 100 ? 350 g a1229 t a = 25c 200 ? 360 g over operating temperature range 160 ? 400 g 1 typical data are at t a = 25c and v cc = 12 v, and are for design estimations only. 2 1 g (gauss) = 0.1 mt (millitesla). 3 minimum and maximum specifications verified by bench characterization and not guaranteed by allegro final test. 4 c l = oscilloscope probe capacitance. hall effect latch for high temperature operation A1225, a1227 and a1229 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value units package thermal resistance r ja package lt, 1-layer pcb with copper limited to solder pads 180 oc/w package lt, 2-layer pcb with 0.94 in 2 copper each side 78 oc/w package ua, 1-layer pcb with copper limited to solder pads 165 oc/w *additional thermal information available on allegro website. 6 7 8 9 2 3 4 5 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 20 40 60 80 100 120 140 160 180 t a (oc) maximum allowable v cc (v) power derating curve (r ja = 165 oc/w) 1-layer pcb, package ua (r ja = 180 oc/w) 1-layer pcb, package lt (r ja = 78 oc/w) 2-layer pcb, package lt v cc(min) v cc(max) 0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 20 40 60 80 100 120 140 160 180 temperature (c) power dissipation, p d (m w) power dissipation (r ja = 165 o c/w) 1-l ay er pc b , packa ge ua (r j a = 180 o c /w) 1- la ye r pcb , p ackage lt (r ja = 78 o c/w) 2-layer p cb, pa c k age lt hall effect latch for high temperature operation A1225, a1227 and a1229 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
characteristic performance A1225, a1227, and a1229 electrical characteristics 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2 6 10 14 18 22 26 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 2 6 10 14 18 22 26 0 50 100 150 200 250 300 - - - 0 20 40 60 80 100 120 140 160 0 50 100 150 200 250 300 2 6 10 14 18 22 26 60 40 20 average supply current (on) versus supply voltage average supply current (on) versus ambient temperature average supply current (off) versus supply voltage average supply current (off) versus ambient temperature average output saturation voltage versus supply voltage average output saturation voltage versus ambient temperature t a (c) i cc(av) (ma) i cc(av) (ma) i cc(av) (ma) i cc(av) (ma) v out(sat) (mv) v out(sat) (mv) v cc (v) t a (c) v cc (v) t a (c) v cc (v) t a (c) ?40 25 150 t a (c) ?40 25 150 t a (c) ?40 25 150 v cc (v) 3.8 4.5 12 24 v cc (v) 3.8 4.5 12 24 v cc (v) 3.8 4.5 12 24 hall effect latch for high temperature operation A1225, a1227 and a1229 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
A1225 magnetic characteristics 140 160 180 200 220 240 260 280 300 -60 -40 -20 0 20 40 60 80 100 120 140 160 140 160 180 200 220 240 260 280 300 2 6 10 14 18 22 26 -300 -280 -260 -240 -220 -200 -180 -160 -140 -60 -40 -20 0 20 40 60 80 100 120 140 160 -300 -280 -260 -240 -220 -200 -180 -160 -140 2 6 10 14 18 22 280 320 360 400 440 480 520 560 600 -60 -40 -20 0 20 40 60 80 100 120 140 160 280 320 360 400 440 480 520 560 600 2 6 10 14 18 22 26 operate point versus supply voltage operate point versus ambient temperature release point versus supply voltage release point versus ambient temperature switchpoint hysteresis versus supply voltage switchpoint hysteresis versus ambient temperature t a (c) b op (g) b op (g) b rp (g) b rp (g) b hys (g) b hys (g) v cc (v) t a (c) v cc (v) t a (c) v cc (v) v cc (v) 3.8 12 24 v cc (v) 3.8 12 24 v cc (v) 3.8 12 24 t a (c) ?40 25 150 t a (c) ?40 25 150 t a (c) ?40 25 150 hall effect latch for high temperature operation A1225, a1227 and a1229 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
a1227 magnetic characteristics 50 63 75 88 100 113 125 138 150 163 175 -60 -40 -20 0 20 40 60 80 100 120 140 160 -60 -40 -20 0 20 40 60 80 100 120 140 160 50 63 75 88 100 113 125 138 150 163 175 2 6 10 14 18 22 26 -175 -163 -150 -138 -125 -113 -100 -88 -75 -63 -50 -175 -163 -150 -138 -125 -113 -100 -88 -75 -63 -50 2 6 10 14 18 22 26 100 125 150 175 200 225 250 275 300 325 350 -60 -40 -20 0 20 40 60 80 100 120 140 160 100 125 150 175 200 225 250 275 300 325 350 2 6 10 14 18 22 26 operate point versus supply voltage operate point versus ambient temperature release point versus supply voltage release point versus ambient temperature switchpoint hysteresis versus supply voltage switchpoint hysteresis versus ambient temperature t a (c) b op (g) b op (g) b rp (g) b rp (g) b hys (g) b hys (g) v cc (v) t a (c) v cc (v) t a (c) v cc (v) v cc (v) 3.8 12 24 v cc (v) 3.8 12 24 v cc (v) 3.8 12 24 t a (c) ?40 25 150 t a (c) ?40 25 150 t a (c) ?40 25 150 hall effect latch for high temperature operation A1225, a1227 and a1229 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
a1229 magnetic characteristics 80 90 100 110 120 130 140 150 160 170 180 190 200 - 60 - 40 - 20 0 20 40 60 80 100 120 140 80 90 100 110 120 130 140 150 160 170 180 190 200 2 6 10 14 18 22 26 -200 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 - 90 - 80 - 60 - 40 - 20 0 20 40 60 80 100 120 140 -200 -190 -180 -170 -160 -150 -140 -130 -120 -110 -100 - 90 - 80 2 6 10 14 18 22 26 160 180 200 220 240 260 280 300 320 340 360 380 400 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 160 180 200 220 240 260 280 300 320 340 360 380 400 2 6 10 14 18 22 26 operate point versus supply voltage operate point versus ambient temperature release point versus supply voltage release point versus ambient temperature switchpoint hysteresis versus supply voltage switchpoint hysteresis versus ambient temperature t a (c) b op (g) b op (g) b rp (g) b rp (g) b hys (g) b hys (g) v cc (v) t a (c) v cc (v) t a (c) v cc (v) v cc (v) 3.8 12 24 v cc (v) 3.8 12 24 v cc (v) 3.8 12 24 t a (c) ?40 25 150 t a (c) ?40 25 150 t a (c) ?40 25 150 hall effect latch for high temperature operation A1225, a1227 and a1229 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
functional description and application information switching behavior the output of the A1225, a1227, and a1229 devices switches low (turns on) when a magnetic field perpendicular to the hall element exceeds the operate point threshold, b op (see figure 1). after turn-on, the output is capable of sinking 25 ma and the output voltage is v out(sat) . notice that the device latches; that is, a south pole of sufficient strength towards the branded surface of the device turns the device on, and the device remains on with removal of the south pole. when the magnetic field is reduced below the release point, b rp , the device output goes high (turns off). the difference between the magnetic operate point and release point is the hysteresis, b hys , of the device. this built-in hysteresis allows clean switch- ing of the output, even in the presence of external mechanical vibration and electrical noise. when the device is powered-on in the hysteresis range, less than b op and higher than b rp , the device output goes high. the correct output state is attained after the first excursion beyond b op or b rp . application information the simplest form of magnet that will operate these devices is a ring magnet, as shown in figure 2. other methods of operation are possible. in three-wire applications the device output is connected through a pull-up resistor to the supply pin or separate battery voltage (figure 3). switching of the output signal indicates sufficient change of the magnetic field. b op b rp b hys v cc v out v out(sat) switch to low switch to high b+ b? v+ 0 figure 1. output switching characteristics figure 2. typical magnetic target configuration using a ring magnet figure 3. typical 3-wire application circuit a122x vout gnd c bypass c l (optional) v pullup v+ r pullup vcc device output hall effect latch for high temperature operation A1225, a1227 and a1229 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
figure 4. chopper stabilization technique chopper stabilization technique when using hall-effect technology, a limiting factor for switchpoint accuracy is the small signal voltage developed across the hall element. this voltage is disproportionally small relative to the offset that can be produced at the output of the hall sen- sor ic. this makes it difficult to process the signal while main- taining an accurate, reliable output over the specified operating temperature and voltage ranges. chopper stabilization is a unique approach used to minimize hall offset on the chip. allegro employs a patented technique to remove key sources of the out- put drift induced by thermal and mechanical stresses. this offset reduction technique is based on a signal modulation-demodula- tion process. the undesired offset signal is separated from the magnetic field-induced signal in the frequency domain, through modulation. the subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at base band, while the dc offset becomes a high-frequency signal. the magnetic-sourced signal then can pass through a low-pass filter, while the modulated dc offset is suppressed. in addition to the removal of the thermal and stress related offset, this novel technique also reduces the amount of thermal noise in the hall sensor ic while completely removing the modulated residue resulting from the chopper operation. the chopper stabilization technique uses a high-frequency sampling clock. for the demodulation process, a sample-and-hold tech- nique is used. this high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal- processing capability. this approach desensitizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent hall output voltages and precise recoverability after temperature cycling. this technique is made possible through the use of a bicmos process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sample-and-hold circuits. amp regulator clock/logic hall element tuned filter anti-aliasing lp filter hall effect latch for high temperature operation A1225, a1227 and a1229 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
hall effect latch for high temperature operation A1225, a1227 and a1229 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package lt 3-pin sot-89 d active area depth, 0.77 mm hall element; not to scale d e e e e 1.14 2.24 b parting line 3 2 1 a c a 10 ref 10 ref 6 ref gate and tie bar burr area b 1.04 0.15 2.16 ref 0.38 min 1.73 0.10 2x 1.50 nom reference land pattern layout; all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances 4.47 +0.13 ?0.08 2.57 +0.03 ?0.28 4.14 +0.10 ?0.20 0.41 +0.03 ?0.06 0.51 +0.05 ?0.07 0.43 +0.05 ?0.07 1.45 +0.15 ?0.05 branding scale and appearance at supplier discretion standard branding reference view nn 1 = supplier emblem n = last two digits of device part number branded face for reference only; not for tooling use (reference dwg-9064) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown updated package drawing only. allegro package assembly tooling has not changed. 1.50 1.20 0.80 2.60 2.00 2.50 0.70 4.60 c pcb layout reference view basic pads for low-stress, not self-aligning additional pad for low-stress, self-aligning additional area for ipc reference layout
hall effect latch for high temperature operation A1225, a1227 and a1229 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com for the latest version of this document, visit our website: www.allegromicro.com copyright ?2009-2010, allegro microsystems, inc. the products described herein are manufactured under one or more of the following u.s. patents: 5,619,137; 5,621,319; 7,425,821 and other patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes no re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. 23 1 1.27 nom 2.16 max 0.51 ref 45 c 45 0.79 ref b e e e 2.04 1.44 gate burr area a b c dambar removal protrusion (6x) a d e d branding scale and appearance at supplier discretion hall element, not to scale active area depth, 0.50 mm ref for reference only; not for tooling use (reference dwg-9049) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar pr o exact case and lead configuration at supplier discretion within l standard branding reference view = supplier emblem n = last two digits of device part number nn 1 mold ejector pin indent branded face 4.09 +0.08 ?0.05 0.41 +0.03 ?0.06 3.02 +0.08 ?0.05 0.43 +0.05 ?0.07 15.75 0.51 1.52 0.5 package ua 3-pin sip

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